64 custom designed ARMv8 “Xiaomi” core up to 2.0 GHz
    Cache – L1 I-Cache and D-Cache, 32MB L2 cache, 128MB L3 Cache
    Memory – 16 DDR3-1600 channels
    ECC and memory protection on all caches, tags and TLBs
    Expansion – 2x 16-lane PCIe 3.0 interfaces
    Performance – 512GFLOPS, 204 GB/s memory bandwidth, 32GB/s I/O bandwidth
    Manufacturing process – 28 nm
    Die size / Package – 640 mm2; FCBGA package with ~3,000 pins
    TDP – 120 Watts